A Reduced-Complexity Fast GPS Receiver using a Systolic Architecture

This paper presents a new structure for fast GPS receivers. The suggested GPS acquisition scheme leverages a systolic-based array structure of regular and simple locally-connected processing-elements (PEs). The new GPS system is simulated and its complexity is evaluated for a real-time implementation on a field programmable gate array (FPGA). The proposed systolicbased acquisition system promises high performance for GPS receivers by yielding greatly improved processing latency and estimation precision while offering an efficient and flexible implementation of a significantly reduced complexity of a fully pipelined architecture.